During the process of developing a circuit design, the behavior of the design is simulated based on a specification of the circuit design. Simulating the design helps to verify correct behavior prior to physical implementation of the circuit. Wasted manufacturing costs due to faulty design may thereby be avoided. Numerous tools are available for simulating circuit designs including, for example, high-level modeling systems (HLMS) and hardware description language (HDL) simulators.
An HLMS is a software tool in which electronic designs can be described, simulated, and translated by machine into a design realization. In an HLMS-based design, there may be some components external to the HLMS environment that under certain circumstances, are desirable to have controlled by and involved in HLMS simulations. For example, it is sometimes useful to take existing HDL components that have been designed using a tool separate from the HLMS and incorporate the HDL components into an HLMS simulation environment. Furthermore, there may be existing hardware components that are desirable to involve in the HLMS simulation. The process of incorporating one or more external components into an HLMS-based simulation is referred to as HLMS co-simulation.
Example co-simulation platforms include both software-based and hardware-based systems. In a software-based system, for example, a portion of the design is simulated with software running on a workstation. In a hardware-based system, a portion of the design is emulated on a hardware platform that includes programmable logic circuitry such as that contained on a field programmable gate array (FPGA) or other types of programmable logic devices (PLDs).
In order to emulate a portion of a circuit design in hardware, the designer must configure the programmable logic circuitry to operate according to the desired portion of the circuit design and configure the simulation system to interface with the targeted programmable logic circuitry. This further may require the designer to modify the underlying hardware description language (HDL) code of the HLMS design. This may present a substantial barrier for a designer seeking to exploit the advantages of co-simulation during routine simulation and debugging.